Generally, new developments in, technology allow electronic device to provide increased functionally in a smaller package. For example, digital cameras, camera phones, movie picture experts group layer three (MP3) complaint audio devices, IPODs®, miniature personal computers, and movie cameras are ever increasing in features and ever decreasing in size. The electronic devices listed above, generally require a significant amount of memory, and thus typically require a significant number of memory integrated circuits (IC)s or memory chips. Accordingly, incorporating a larger number of ICs into smaller packages continues to be a design goal for many.
Packaging and interconnecting a large number of ICs within a sophisticated, high density electronic device, such as a camera phone presents many design challenges. Such design challenges include electrically interconnecting the ICs in tight spaces, allowing for adequate cooling of the ICs, and ensuring that vibration and thermal expansion due to heating does not break or fracture the electrical interconnections between the devices.
Advances in technology and in manufacturing equipment have allowed ICs to become physically larger in size. Generally, the larger the IC, the more functions and features that the IC can provide. However, there is a practical and/or economic limit to the maximum size of an IC. For example, as the die on which the IC gets manufactured gets larger, the reliability or yield of each batch of ICs on each wafer can significantly decrease. Second, semiconductor manufacturing equipment often has limitations regarding the maximum size of the die that it can cut from a wafer and handle during the manufacturing and testing process. Third, testing and assembling large die requires specialized manufacturing and testing equipment.
Thus, for physically larger ICs, not only is the number of ICs that can be manufactured on wafer reduced, but the yield from each wafer is typically greatly reduced. Low yields greatly increase the cost of individual IC devices, because the cost to manufacture the wafer must be allocated to the few acceptable IC devices produced. Because larger die are generally much more expensive, designers continue to work on ways to efficiently interconnect several smaller IC die.
To reduce the size of electronic devices, achieve the desired functionality, and provide an economical product, designers commonly utilize smaller ICs and tightly package the IC's on circuit boards within the device. Even relatively small ICs have hundreds of conductive pads that must be electrically interconnected to the circuit board such that the IC die can receive power, ground, data and control signals from other ICs. It can be appreciated that efficiently and reliably interconnecting hundreds of pads between multiple ICs in a small package can be a complex process.
Many vendors stack ICs horizontally or in a parallel configuration with the mounting circuit board and with other ICs. For example, is it common for a state-of-the-art device to have four ICs stacked on top of each other in various locations on a circuit board. In such a configuration multiple individual cables are looped from IC to IC to interconnect the ICs, and a stack of four IC die often requires precision assemble of six or more individual cables.
Some manufacturers place the IC die in chip carriers, glue and wire-bond the die to the chip carrier and place the solder pads of the chip carrier on the outside or periphery of the actual chip carrier. This makes the packaged IC actually larger than a configuration where the pads are placed directly underneath the individual die and no chip carriers are utilized. Others utilize “flip chip technology where the chip is a surface mounted to an organic chip carrier and again the pads are often placed on the outside edge of the chip carrier.
Interconnecting stacked IC creates many design challenges. For example impedance matching of conductors, robust solder connections, mechanical retention of the ICs and efficient assembly of these IC packages are all important considerations. More particularly, it is tedious task to make electrical connections from “microscopic” pads on an IC die to other ICs.
As stated above, in most electronic devices there is an ever increasing need for memory capacity and most new devices require a significant number of memory ICs. Generally, memory systems can require duplicate or numerous busses and conductive paths. Such a design requires twice the routing density than conventional designs. Most designers find it very challenging to assemble and interconnect so many ICs in such limited space and provide compact impedance matched routing for the electrical signals.